Programmable devices may include, but are not limited to, programmable logic devices (PLDs), which are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional programmable resources with special purposes (e.g., DLLs, RAM, DSP blocks, multipliers, processors, transceivers).
The CLBs, IOBs, interconnect, and other programmable resources are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, interconnect, and other blocks are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the complex programmable logic device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in programmable logic arrays (PLAs) and programmable array logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits (configuration data or bitstream) provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., flash memory, as in some CPLDs), or in any other type of memory cell.
In particular, some programmable devices, including many FPGAs, have internal volatile memory (e.g., SRAM configuration memory) for storing the configuration data or bitstream during operation of the FPGA. Since the internal volatile memory does not retain data when power is not supplied to the device, such programmable devices typically have an external device for providing the bitstream at power up or on reset conditions. The external device may be an external tester/programmer, such as a computer or test fixture, or an external nonvolatile memory, such as a flash or EEPROM memory.
Prior techniques for configuring a programmable device, such as n FPGA, have used a serial interface to the external device. For example, serial memories may be popular because they have a very compact interface with a small number of pins. However, a memory having a parallel interface may offer significant speed increases that allow a programmable device to be configured in a short amount of time. Parallel memories may also be more economical and may be available in larger sizes than their serial counterparts. Prior parallel techniques have had certain constraints, such as board layout constraints or timing constraints, that have limited their appeal.
Therefore, it would be desirable to address these and other needs in programmable devices.